1. Van der Waals intergration and heterostructures for micro/nanoelectronics and optoelectronics

Van der Waals (vdW) integration, in which pre-formed building blocks are physically assembled together through weak vdW interactions, offers an alternative low-energy material integration approach. Such physical assembly method does not rely on one-to-one chemical bonds or does not involve direct chemical processing on existing materials, thus is not limited to materials that have similar lattice structures or require compatible synthetic conditions. It, therefore, has attracted considerable interest for integrating diverse materials with highly distinct lattice structure yet little chemical disorders at the interface.

Without the lattice match or processing compatibility requirement, such bond-free integration approach is not limited to a particular material dimension, and could be generally applicable for flexible integration of radically different materials with distinct crystal structures (crystallinity, lattice symmetry, lattice constant), electronic properties (metals, semiconductors, insulators and superconductors), or material dimensions (0D, 1D, 2D and 3D). We hope to extend this vdW stacking technique to various 3D material systems or hetero-structures that are previously limited by the interface disorder,  opening up new opportunities for fundamental studies and enabling unprecedented device functions or performance.


2. High performance and low power field effect transistors based two-dimensional channel material

Each layer in two-dimensional semiconductors (2DSC) consists of a single- or few-atom-thick, covalently bonded lattice, in which all carriers are confined in their atomically thin channel with superior gate controllability and greatly suppressed OFF-state current, in contrast to typical bulk semiconductors plagued by short channel effects and heat generation from static power. Additionally, 2DSC are free of surface dangling bonds that plague traditional semiconductors, and hence exhibit excellent electronic properties at the limit of single atom thickness. Therefore, 2DSCs can offer significant potential for the ultimate transistor scaling to single atomic body thickness. Earlier studies of graphene transistors have been limited by the zero bandgap and low ON–OFF ratio of graphene, and transition metal dichalcogenide (TMDC) devices are typically plagued by insufficient carrier mobility, and large contact resistances. To this end,  we are devoting considerable efforts towards searching for new 2DSCs with optimized contact behavior. We hope to use this atomic thin membranes as the a complementary channel materials (as for silicon) for low-power (LP) logic applications.


3. Flexible vertical thin film transistors for macro-electronic and display application

Thin film transistors (TFTs) represent the fundamental device building blocks for macroelectronics that requires the distribution of functional electronic components over large area. Flexible plastic is becoming the preferred substrate for macroelectronic applications because of their lightweight, flexibility, short resistance, and low cost.  To ensure the compatibility with flexible plastics and to mitigate the cost in large area fabrication, current TFT technologies normally adopt lower performance materials (typically amorphous or polycrystalline materials processed at low temperature), and lower resolution lithography (typically with tens micrometer transistor channel length) with the resulting devices typically having relatively poor electrical performance or insufficient mechanical robustness.

By using graphene as a unique work function tunable contact, we could fabricate a unique vertical thin film transistor architecture, where the ultra-short channel lengthcan be automatically fabricated ( <10 nm as determined by the thickness of the  thin film rather than by lithography resolution) to afford a delivering current greatly exceeding that of the conventional planar TFTs.  Furthermore, unlike conventional planar inorganic TFTs in which any cracks in the channel can severely degrade the lateral charge transport, the vertical (out-of-plane) current flow in the vertical TFT is largely unaffected by the in-plane cracks. We hope to to study the electrical and mechanical properties of  verticle TFTs, to enable a new generation of highly flexible macroelectronics with exceptional electrical and mechanical performance.



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